1. Field of the Invention
Example embodiments of the present invention relate in general to a tape wiring substrate and a tape package using the tape wiring substrate and, more particularly, to a tape wiring substrate that may have a dual metal layer and a chip-on-film package that may implement the tape wiring substrate.
2. Description of the Related Art
Flat panel displays may include, for example, a liquid crystal display (“LCD”) for portable phones, a thin-film transistor liquid crystal display (“TFT LCD”) for computers and plasma display panels (“PDP”) for domestic use. A flat panel display may include a component part known in the art as a tape package. In some applications, the tape package may have fine pitch wiring patterns.
Tape packages may include a tape wiring substrate. The two principal types of tape packages may be a tape carrier package (“TCP”) and a chip on film (“COF”) package. The tape wiring substrate of a TCP may have a chip mounting window in which a semiconductor chip may be mounted via an inner lead bonding method (for example). The tape wiring substrate of a COF package may not include a chip mounting window. Here, the semiconductor chip may be flip chip bonded to the tape wiring substrate. As compared to the TCPs, the COF packages may allow a thinner tape wiring substrate and/or finer pitch wiring patterns.
In the COF packages, I/O terminal patterns may act as external connection terminals, instead of solder bumps. The I/O terminal patterns may be directly attached to a printed circuit board or a display panel.
FIG. 1 is a plan view of a conventional COF package 100. FIG. 2 is a cross-sectional view taken along the line II-II of FIG. 1.
Referring to FIGS. 1 and 2, the COF package 100 may include a tape wiring substrate 20. A semiconductor chip 10 may be flip chip bonded to the tape wiring substrate 20. A molding compound 40 may seal the flip chip bonded portion through an underfill process.
The semiconductor chip 10 may have an active surface that may support electrode pads 12. The electrode pads 12 may be provided along the edge portions of the active surface. Electrode bumps 16 may be provided on the electrode pads 12. The electrode bumps 16 may include input bumps 17 and output bumps 18, for example. The input bumps 17 may include ground bumps 17a and power bumps 17b, for example.
The tape wiring substrate 20 may include a base film 21, and an upper metal layer 24 provided on the upper surface 22 of the base film 21. The base film 21 may have a chip mounting area confronting the semiconductor chip 10. The chip mounting are may be located in the center portion of the base film 21. The base film 21 may include sprocket holes 29. The sprocket holes 29 may be arranged along the base film 21 at predetermined intervals. An end of the upper metal layer 24 may be connected to the electrode bumps 16. Another end of the upper metal layer 24 may extend outwards from the chip mounting area. The upper metal layer 24 may include input terminal patterns 25 and output terminal patterns 26. The input terminal patterns 25 may include input terminal patterns for ground 25a (“ground terminal patterns”) and input terminal patterns for power 25b (“power terminal patterns”). The input terminal patterns 25 may extend to one side of the base film 21 relative to the semiconductor chip 10, and the output terminal patterns 26 may extend to another side of the base film 21 relative to the semiconductor chip 10. The input and the output terminal patterns 25 and 26 may extend parallel to the arrangement of the sprocket holes 29.
When the semiconductor chip 10 is flip chip bonded to the tape wiring substrate 20, the ground bumps 17a may be bonded to the ground terminal patterns 25a and the power bumps 17b may be bonded to the power terminal patterns 25b. 
Although conventional COF packages are generally thought to be acceptable, they are not without shortcomings. For example, to facilitate achievement of semiconductor products having lighter weight, smaller size, higher speed, multifunction and/or increased performance, the upper metal layer 24 may have fine pitch wiring patterns, the semiconductor chip 10 may be more miniaturized, and the number of electrode bumps 16 may be increased. Accordingly, the ground terminal patterns 25a and the power terminal patterns 25b may be reduced in pitch. The ground and the power terminal patterns 25a and 25b provided on the upper surface 22 of the base film 21 may have insufficient areas for stable ground and/or power supply, for example.
The conventional COF package 100 may insufficiently reduce electromagnetic waves and/or noise that may occur during operation of the semiconductor chip 10, which may result in poor electromagnetic interference and/or noise characteristics. Further, the conventional COF package 100 may unstably supply power to the semiconductor chip 10.